JPH0127612B2 - - Google Patents

Info

Publication number
JPH0127612B2
JPH0127612B2 JP1565580A JP1565580A JPH0127612B2 JP H0127612 B2 JPH0127612 B2 JP H0127612B2 JP 1565580 A JP1565580 A JP 1565580A JP 1565580 A JP1565580 A JP 1565580A JP H0127612 B2 JPH0127612 B2 JP H0127612B2
Authority
JP
Japan
Prior art keywords
control signal
mos transistor
circuit
whose gate
transistor whose
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1565580A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56112125A (en
Inventor
Takashi Umezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1565580A priority Critical patent/JPS56112125A/ja
Publication of JPS56112125A publication Critical patent/JPS56112125A/ja
Publication of JPH0127612B2 publication Critical patent/JPH0127612B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP1565580A 1980-02-12 1980-02-12 Logical circuit Granted JPS56112125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1565580A JPS56112125A (en) 1980-02-12 1980-02-12 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1565580A JPS56112125A (en) 1980-02-12 1980-02-12 Logical circuit

Publications (2)

Publication Number Publication Date
JPS56112125A JPS56112125A (en) 1981-09-04
JPH0127612B2 true JPH0127612B2 (en]) 1989-05-30

Family

ID=11894730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1565580A Granted JPS56112125A (en) 1980-02-12 1980-02-12 Logical circuit

Country Status (1)

Country Link
JP (1) JPS56112125A (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4451922A (en) * 1981-12-21 1984-05-29 Ibm Corporation Transmission logic parity circuit
JPS62293426A (ja) * 1986-06-12 1987-12-21 Matsushita Electric Ind Co Ltd 一致検出回路

Also Published As

Publication number Publication date
JPS56112125A (en) 1981-09-04

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